Architecting Low Power Crossbar-Based Memristive RAM

Crossbar-based memristive arrays are promising candidates for future high-density, low-power memories. Their structural simplicity allows them to be fabricated with pitches as small as 17 nm [6] and with projected reductions, according to the ITRS, to a few nanometers in the next decade [1]. A crossbar is particularly useful if two-terminal switching nano-devices with a nonlinear behavior are placed at each crosspoint and used them as memory and/or computing elements. There have been reported cases of bistable memristive devices [4, 3] that are suitable for such crossbar implementations. With pitches of 2Fnano, each nano-device in a crossbar will have a footprint of 4F 2 nano which can potentially be reduced to 4F 2 nano/L by stacking L crossbar layers. Such footprints translate into memory densities of more than 1012cm−2 bits per crossbar layer and with projected densities exceeding 1013cm−2 bits per layer in the next decade [1]. This contrasts to the footprint of a typical DRAM cell which falls between 6 to 8F 2 cmos (Fcmos is the half-pitch of a given CMOS process). This footprint results into memory densities of 1012cm−2 without significant projected improvements in the next decade according to the ITRS [1].